LU, Zhonghai - HKUST Class Schedule & Quota

Class Schedule & Quota
2025-26 Spring 2025-26 Winter 2025-26 Fall 2024-25 Summer
2025-26 Fall
Common Core Course
The class information on this page will normally be updated every 15 to 20 minutes during class enrollment period.
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This service was first adapted from a student contribution in 2011-12 Fall. The efforts of all concerned are duly acknowledged.

AIAA AMAT BSBE CMAA CNCC CNGF DLED DSAA EOAS FTEC FUNH INFH INTR IOTA IPEN LANG MICS MSSM PDEV PLED ROAS SEEN SMMG SOCH SYSH UCMP UCUG UFUG UGOD

COURSE INFO

VECTOR	[2-0-0:2]
DESCRIPTION	This course covers background knowledge in the thrust areas of the Function Hub, including Advanced Materials, Sustainable Energy and Environment, Microelectronics, and Earth, Ocean and Atmospheric Sciences.

FUNH 5000 - Introduction to Function Hub for Sustainable Future (2 units)

Section	Date & Time	Room	Instructor	Quota	Enrol	Avail	Wait	Remarks
L03 (6123)	Th 10:00AM - 11:50AM	Rm 101, W1	LIU, Zhen LU, Zhonghai YANG, Qichun ZHU, Guoyi	150	148	2	0

COURSE INFO

VECTOR	[2-1-0:3]
DESCRIPTION	The course focuses on the communication problem of on-chip many-core architectures. It introduces basic concepts and principles of on-chip bus and interconnection network, in particular, about network topology, routing and flow control, deadlock/livelock, and quality-of-service (QoS) et cetera. It presents the micro-architecture details of on-chip router and network interface designs for both message passing and shared memory systems. Furthermore, theoretical and experimental performance evaluation methodology will be investigated.

VECTOR

[2-1-0:3]

DESCRIPTION

The course focuses on the communication problem of on-chip many-core architectures. It introduces basic concepts and principles of on-chip bus and interconnection network, in particular, about network topology, routing and flow control, deadlock/livelock, and quality-of-service (QoS) et cetera. It presents the micro-architecture details of on-chip router and network interface designs for both message passing and shared memory systems. Furthermore, theoretical and experimental performance evaluation methodology will be investigated.

MICS 6002I - Network on Chip (3 units)

Section	Date & Time	Room	Instructor	Quota	Enrol	Avail	Wait	Remarks
L01 (6216)	We 01:30PM - 03:20PM	Rm 202, E1	LU, Zhonghai	30	8	22	0
T01 (6217)	We 03:30PM - 04:20PM	Rm 202, E1	LU, Zhonghai	30	8	22	0